In the manufacturing of integrated circuits, after the individual devices, such as the transistors, have been fabricated in the silicon substrate, they must be connected together to perform the desired circuit functions. This connection process is generally called "metalization", and is performed using a number of different photolithographic and deposition techniques.
In one connection process, which is called a "dual damascene" technique, two channels of conductive materials, are positioned in vertically separated planes perpendicular to each other and interconnected by a vertical "via" at their closest point.
The first channel part of the dual damascene process starts with the placement of a first channel dielectric layer, which is typically an oxide layer, over the semiconductor devices. A first damascene step photoresist is then placed over the oxide layer and is photolithographically processed to form the pattern of the first channels. An anisotropic oxide etch is then used to etch out the channel oxide layer to form the first channel openings. The damascene step photoresist is stripped and a thin barrier layer is deposited to line the walls of the first channel opening. This barrier layer acts as a barrier to prevent diffusion of subsequently deposited conductive material into the oxide layer and the semiconductor devices. It also ensures good adhesion and electrical contact of subsequent layers to the underlying semiconductor devices while improving the formation of subsequently deposited conductive material. A seed layer is then deposited on the barrier layer to act as the "seed" for subsequent deposition of the conductive material. A first conductive material is then deposited on the seed layer to fill the channels and vias. The adhesion/barrier layer, the seed layer, and the conductive material are subjected to a chemical-mechanical polishing process which removes the layers and material above the first channel oxide layer and damascenes the first conductive material in the first channel openings to form the first channels.
The via formation step of the dual damascene process starts with the deposition of a thin stop nitride over the first channels and the first channel oxide layer. Subsequently, a separating oxide layer is deposited on the stop nitride. This is followed by deposition of a thin via nitride. Then a via step photoresist is used in a photolithographic process to designate round via areas over the first channels.
A nitride etch is then used to etch out the round via areas in the via nitride. The via step photoresist is then removed, or stripped. A second channel dielectric layer, which is typically an oxide layer, is then deposited over the via nitride and the exposed oxide in the via area of the via nitride. A second damascene step photoresist is placed over the second channel oxide layer and is photolithographically processed to form the pattern of the second channels. An anisotropic oxide etch is then used to etch the second channel oxide layer to form the second channel openings and, during the same etching process to etch the via areas down to the thin stop nitride layer above the first channels to form the vias. The damascene photoresist is then removed, and a nitride etch process removes the nitride above the first channels in the via areas. A barrier layer is then deposited to line the vias and the second channel openings. This is followed by a deposition of the seed layer and then the second conductive material in the second channel openings and the vias to form the second channel and the via. A second chemical-mechanical polishing process leaves the two vertically separated, horizontally perpendicular channels connected by cylindrical vias.
The use of the dual damascene technique eliminates metal etch and dielectric gap fill steps typically used in the metalization process. The elimination of metal etch steps is important as the semiconductor industry moves from aluminum to other metalization materials, such as copper, which are very difficult to etch.
One drawback of using copper is that copper diffuses rapidly through various materials. Unlike aluminum, copper also diffuses through dielectrics, such as oxides. When copper diffuses through dielectrics, it can cause damage to neighboring devices on the semiconductor substrate. To prevent diffusion, materials such as tantalum (Ta), titanium (Ti), and tungsten (W), their alloys or combinations thereof are used as barrier materials for copper.
In vias, copper also has the drawback that it is subject to electro-migration, or movement of copper atoms under the influence of current flow, which can cause voids in the copper. To prevent this, barrier materials are disposed at the bottom of vias above the conductive channels.
A problem associated with the interface between the barrier layer and the copper seed layer is the difficulty bonding the two layers. For example, to provide the excellent bonding of the two layers by intermixing, the two layers must be heated above 400.degree. C. Unfortunately, copper tends to clump, or agglomerate, at temperatures above 400.degree. C. which means that the optimal bonding temperatures can not be used.
The copper seed layers for copper interconnect in a damascene process are typically deposited by physical vapor deposition (PVD) or derivatives of PVD techniques on top of the barrier materials. The preferred method of deposition is by low temperature chemical vapor deposition specifically because of the agglomeration problem.
A solution, which would permit the formation of an intermixed layer has been long sought, but has eluded those skilled in the art. As the semiconductor industry is moving from aluminum to copper and other type of materials with greater electrical conductivity and thinner channels and vias, it is becoming more pressing that a solution be found.